1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device by forming a groove wiring in a low-permittivity (low-k) film.
2. Description of the Related Art
In recent years, attendant on the tendency toward semiconductor devices higher in the degree of integration and minuter in size, a reduction in RC delay has come to be needed especially. In view of this, it has been proposed to use copper (Cu) having a low specific resistance as a wiring material, in place of aluminum (Al) used conventionally, and to use a low-permittivity (low-k) film with a low permittivity as an insulating material. As to low-permittivity (low-k) insulating films, development of insulating films with a relative permittivity k<3.0 has been under way, and examples of such insulating films include hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), and aromatic compound-containing organic insulating film. Hereinafter, the low-permittivity film means an insulating film with a relative permittivity k<3.0.
In recent years, in the wiring structures in which grooves formed in an insulating film are filled up with a wiring material to form wirings (for example, dual Damascene structure), a hybrid structure obtained by combining an aromatic compound-containing insulating film easy to process with polymethylsilsesquioxane (MSQ) has been widely used. In consideration of the 45 nm or 32 nm generation as a design rule, the use of a low-permittivity film with a permittivity of not more than 2.5 as a insulation film to be provided with vias has been proposed. In general, a low-permittivity film is susceptible to plasma damages at the time of processing thereof, and, as a result, tends to be hygroscopic. In addition, since the low-permittivity film often has pores formed therein for reducing the permittivity, and the presence of the pores accelerates absorption of moisture. Where the low-k film is thereafter subjected to a wetting treatment, the pores may form paths through which a chemical liquid penetrates. Besides, the pores may permit a metal to ooze out into the insulation film.
Where absorption of moisture into the insulation film has occurred, corrosion (e.g., oxidation) of the barrier metal film is caused upon degassing, resulting in oozing out of the metal into the insulation film or an increase in the via resistance due to deterioration of the barrier property. In addition, the adhesion between the insulation film and the copper seed layer is also deteriorated, generating such fatal defects as electro-migration and stress migration arising from the vias.
As a countermeasure against the plasma damages to the low-permittivity film, development of a pore-sealing technology has been being made (refer to Non-Patent Document 1 (M. Ueki, M. Narihiro, H. Ohtake, M. Tagami, M. Tada, F. Ito, Y. Harada, M. Abe, N. Inoue, K. Arai, T. Takeuchi, S. Saito, T. Onodera, N. Furutake, M. Hiroi, M. Sekine and Y. Hayashi, “Highly Reliable 65 nm-mode Cu Dual Damascene Interconnects with Full Porous-SiOCH (k=2.5) Films for Low-Power ASICs”, 2004 Symposium on VLSI Technology Digest of Technical Papers p60-61, 2004.)).
In the technology disclosed in Non-patent Document 1, after a low-permittivity film is processed, a sealing material film is built up for the purpose of sealing. In this case, etch-back should be conducted for securing conductivity at the bottom parts of the vias. This makes it possible to secure conductivity at the bottoms of the vias and to leave the sealing material film in the form of spacers in the trenches and on side wall parts of the vias. However, this process has the problem that the bottom parts of the vias cannot be sealed, and the problem that the bottom parts of the vias undergo etching damages during the spacer forming process, resulting in a rise in the interlayer capacity (refer to Non-patent Document 2 (S. Arakawa, I. Mizuno, Y. Ohoka, K. Nagahata, K. Tabuchi, R. Kanamura and S. Kadomura, “Breakthrough Integration of 32 nm-mode Cu/Ultra Low-k SiOC (k=2.0) Interconnects by using Advanced Pore-Sealing and Low-k Hard Mask Technologies”, 2006 IEEE p210-212, 2004.)). These problems become more conspicuous as the lowering in the permittivity of the insulation film is accelerated.
In order to solve the above problems, elimination of the etch-back step may be contemplated as a method for attaining the object. It is considered that via conduction can be secured to a certain extent by reducing the deposited film thickness to a level of several nanometers. In this case, however, the coverage of the side wall parts would be insufficient, and the sealing effect would be deficient, resulting in deteriorated reliability.
An example of the method of manufacturing a wiring structure by use of a low-permittivity film in the related art will be described below, referring to manufacturing step sectional views shown in FIGS. 6A to 6I.
As shown in FIG. 6A, a wiring groove 251 is formed in an insulating film (not shown) formed on a semiconductor substrate (not shown), and a wiring 253 is formed inside the wiring groove 251, with a barrier metal layer 252 therebetween. For example, the wiring 253 is formed from copper (Cu) in a thickness of 60 nm. Next, a barrier layer 254 covering the wiring 253 is formed. The barrier layer 254 is composed of a silicon carbonitride (SiCN) film formed by a chemical vapor deposition (e.g., PE-CVD: plasma enhancement CVD) method, and is formed in a thickness of 30 nm. Subsequently, a insulation film 211 is formed. The insulation film 211 is composed, for example, of an MSQ (methyl-hydrogen-silsesquioxane)-based porous film having a permittivity of not more than 2.5, the thickness being 250 nm. The insulation film 211 may be formed by a CVD method or by an SOG coating method. In addition, the material of the wiring 253 is not limited to copper but may be other metal such as silver (Ag), gold (Au) and aluminum (Al).
Next, as shown in FIG. 6B, an etching mask 231 for forming a via is formed on the insulation film 211 by use of a chemical amplification type ArF resist. The diameter of a via pattern 232 formed in the etching mask 231 was 60 nm.
Subsequently, as shown in FIG. 6C, by dry etching conducted using the etching mask 231 [see FIG. 6B], a via hole 213 is formed in the insulation film 211. In the dry etching, a carbon fluoride (CFx)-based gas was used as the etching gas. Thereafter, the etching mask 231 is removed by ashing with an oxygen (O2)-based gas. This etching treatment is carried out at a low pressure so as to minimize the plasma damages to the insulation film 211, which is a low-permittivity (low-k) film. In this case, the gas pressure was set to 0.27 Pa, and is desirably not more than 0.67 Pa.
Next, as shown in FIG. 6D, an etching mask 233 for forming wiring grooves is formed on the insulation film 211 by use of a chemical amplification type ArF resist. The width of wiring groove patterns 234 formed in the etching mask 231 was 60 nm.
Subsequently, as shown in FIG. 6E, by dry etching conducted using the etching mask 233 [see FIG. 6D], wiring grooves 214 are formed in a depth of 140 nm in the insulation film 211. In this dry etching, a carbon fluoride (CF)-based gas was used as the etching gas. Thereafter, the etching mask 233 is removed by ashing with an oxygen (O2)-based gas. This treatment is carried out at a low etching atmosphere pressure so as to minimize plasma damages to the low-permittivity (low-k) film. The pressure of the etching atmosphere was set to 0.27 Pa.
Next, as shown in FIG. 6F, the barrier layer 254 at a bottom part of the via hole 213 is removed, to expose the wiring 253 there. The etching for this removal is conducted using a carbon fluoride (CF)-based gas. Further, the surface of the wiring 253 thus exposed is washed with an organic cleaning liquid.
Subsequently, as shown in FIG. 6G, a seal layer 215 having a thickness of 1 nm or below is formed on inside surfaces of the via hole 213 and the wiring grooves 214 by using dimethylphenylsilane (DMPS) as a precursor. This treatment was carried out under the conditions of a substrate RF bias power of 150 W, a film forming atmosphere pressure of 0.67 kPa, a flow rate of DMPS as precursor of 500 cm3/min, a flow rate of helium (He) as carrier gas of 1000 cm3/min, and a substrate temperature of 350° C., but these conditions are not limitative.
Next, as shown in FIG. 6H, a tantalum (Ta) film having a thickness of 7 nm is formed as a barrier layer 216 on the surface of the insulation film 211 inclusive of the inside surfaces of the via hole 213 and the wiring grooves 214, with the seal layer 215 therebetween, by a sputtering method. Further, a copper seed layer (not shown) is formed in a thickness of 45 nm. Subsequently, the inside of the via hole 213 and the wiring grooves 214 is filled up with a copper (Cu) film 217 by an electrochemical plating (ECP) method or a CVD method. Next, an annealing treatment for grain growth is conducted at 250° C. for 90 sec. Subsequently, the surplus copper (Cu) film 217 (inclusive of the copper seed layer) on the insulation film 211 is polished away by a chemical mechanical polishing (CMP) method, to complete copper wirings 218 in which the via hole 213 and the wiring grooves 214 are filled up with the copper film 217, with the barrier film 216 therebetween, and which are connected to the wiring 253 through the via hole 213.
After the dual Damascene process as above-mentioned, the insulation film 211 which is a low-permittivity film has received much plasma damages, the surface layer damaged part has absorbed moisture, and absorption of moisture into the film through pores has progressed.
In the case where the thickness of the seal layer 215 is 1 nm, the resistance (mean value) is raised by 50%, and the dispersion of resistance is also increased by a factor of 3 or more, as compared with the case where the sealing treatment is not conducted. This is not permissible on a device design basis. Besides, in the case where the thickness of the seal layer 215 is 0.5 nm, defects are generated upon the subsequent test of reliability (stress migration, electro-migration). This is considered to show that the small thickness of the seal layer 215 made the sealing effect insufficient, so that film quality deterioration (oxidation) of the barrier metal proceeded due to degassing from the inside of the film, oozing-out of copper (Cu) is observed, and, as shown in FIG. 6I, the adhesion between the copper (Cu) seed layer and the insulation film was deteriorated, resulting in the defect composed of formation of a void 219 inside the via hole 213.